1. Technical Field of the Invention
The present invention relates to integrated circuits and, in particular, to a bias circuit for a programmable storage cell that utilizes a floating-gate transistor as a storage unit.
2. Description of Related Art
Read-only memories are commonly organized in matrix form, utilizing rows and columns. The rows are referred to as bit rows, and the columns are referred to as word columns. Each intersection of a row and column forms a storage cell whose electrical state represents an information element. Depending on the technology used, these storage cells are programmable one or more times, and they can be erased individually or comprehensively.
The rows and the columns of the memories are generally tested following production to ensure that access can be made to all the storage cells of the memories and that each cell can be programmed and erased in such a way that there is definite knowledge, at any time, of the electrical state of the storage cells.
A programmable memory circuit typically comprises a floating-gate transistor, commonly called a fuse, that is series-connected with a current source. Each floating-gate transistor represents one address bit. Depending on the electrical state of the floating-gate transistor (i.e., whether there are electrons present at its gate), the fuse behaves like an open circuit or like a resistor. If it behaves like a resistor, it may conduct current. On the contrary, if it behaves like an open circuit, it can not conduct current. A current detector may then be used to read the data stored therein by detecting the currents flowing at each fuse.
Reference is now made to FIG. 1 wherein there is shown an integrated circuit 1 in accordance with U.S. Pat. No. 5,900,756. The circuit 1 includes a plurality of storage circuits 2 (not all of which are represented). Each storage circuit 2 includes a cell referred to as a fuse. More specifically, the fuse is a floating-gate transistor 3 that is series connected with an N type isolation transistor 4 between a reference terminal 5 and a supply terminal 6. Typically, the reference terminal 5 gives a ground potential GND and the supply terminal 6 gives a positive supply potential VCC of the order of some volts (for example, five volts).
The floating-gate transistor 3 is connected through its control gate, by means of a circuit (not explicitly shown), to either the ground potential GND or the supply potential VCC. The source of transistor 3 is connected to the ground terminal 5 and the drain of transistor 3 is connected to the source of the isolation transistor 4. The isolation transistor 4 has its drain connected through a resistor 25 to the supply terminal 6.
A programming and reading circuit 7 is connected to the drain of the floating-gate transistor 3 and is also connected to the drain of the isolation transistor 4. In a first mode of operation referred to as a xe2x80x9cprogramming mode,xe2x80x9d the circuit applies a voltage of some volts to the floating-gate transistor 3, with the control gate of this transistor 3 being connected to ground. In a second mode of operation referred to as a xe2x80x9creading mode,xe2x80x9d the circuit 7 detects a possible passage of current through resistor 25 and hence into the floating-gate transistor 3. This passage of current depends on the electrical state of the floating-gate transistor 3 (namely the presence or non-presence of electrons on the floating gate),.
More specifically, the circuit 2 operates in the following manner:
in programming mode, depending on the electrical state desired, a high value (for example, 10 volts) is applied (or not applied) on the drain of the floating-gate transistor in order to inject (or not inject) electrons into the floating gate, the control gate of the floating gate transistor is connected to ground, and the control gate of the isolation transistor is also connected to ground; and
in reading mode (i.e., current passage detection to read the addressed bit), the N type isolation transistor is biased positively at its control gate in order to be turned on, and the control gate of the floating-gate transistor is connected to a positive supply potential VCC given by the supply terminal.
When configured in the reading mode, the isolation transistor is on and a current may flow, as the case may be, depending on the electrical state of the floating-gate transistor. The isolation transistor is used to impose a constant voltage on the drain of the floating-gate transistor to have the same reading conditions whatever the current given by the supply terminal. In this case, the current read is only a function of the threshold voltage of the floating-gate transistor, and this threshold voltage varies according to the electrical state of this transistor.
To impose a constant voltage on the drain of the floating-gate transistor, a constant bias voltage is imposed on the isolation transistor. This bias voltage is typically twice the threshold voltage Vt of the isolation transistor (wherein typically Vt is approximately one volt). A low bias voltage is chosen in order to limit the current produced and hence the consumption of the circuit.
A bias circuit, capable of giving adequate voltage in programming mode (for the connection to the ground of the control gate of the isolation transistors), is accordingly needed to operate the circuit 2. Irrespective of the mode of operation in effect, the bias circuit must provide the proper bias voltage. This is the case, for example, in a watch mode of operation wherein the memory is supplied with bias but is not currently being used for reading or writing. It is preferable that the bias circuit operate as quickly as possible during the activation of the memory (for example, when reading and writing).
The integrated circuit 1 accordingly includes a first bias circuit 8 having a control terminal 10 and an output terminal 11. The first bias circuit 8 is formed by two arms, each arm consisting of series-connected transistors between the supply terminal 6 and the ground terminal 5. A first arm 12 has a P type transistor 14a whose source is connected to the supply terminal 6 and whose drain is connected to the drain of an N type transistor 15a.The source of the N type transistor 15a is connected to the drain and to the control gate of an N type transistor 16a, configured as a diode, with the source of transistor 16a being connected to the ground terminal 5. The second arm 13 of the first bias circuit 8 similarly includes a P type transistor 14b whose source is connected to the supply terminal 6 and whose drain is connected to the drain of an N type transistor 15b. The source of this N type transistor 15b is connected to the drain and to the control gate of an N type transistor 17, configured as a diode. The source of the transistor 17 is connected to the drain and to the control gate of an N type transistor 16b, also configured as a diode, with the source of transistor 16b being connected to the ground terminal 5. The control gates of the P type transistors 14a and 14b are connected to each other and to the control terminal 10. The control gate of the N type transistor 15b of the second arm 13 is connected to the drain of the P type transistor 14a of the first arm 12. The control gate of the N type transistor 15a of the first arm 12 is connected to the source of the N type transistor 15b of the second arm 13. The source of transistor 15b is further connected to the output terminal 11. The first bias circuit 8 further includes an N type transistor 18 mounted at the output between the output terminal 11 and the ground terminal 5. This output N type transistor 18 has its control gate connected to the control terminal 10.
A brief description of the operation of the first bias circuit 8 will now be provided. The control terminal 10 receives a first binary control signal VB0. The output terminal 11 supplies a binary bias voltage VB to the storage circuits 2. This bias voltage VB takes a first binary value when the first control signal VB0 is in a first state (VB0=1) and a second binary value when the first control signal VB0 is in a second state (VB0=0).
If Vt designates the threshold voltage of the isolation transistor 4, then the first binary value of VB is equal to the ground potential GND and the second binary value of VB is equal to 2*Vt. The first binary value of VB corresponds to an operation that isolates the floating-gate transistor 3 from the current source formed by the resistor 25 and the supply terminal 6 (for use in programming mode operation). The second binary value of VB corresponds to an operation that connects the floating-gate transistor 3 to this current source (for use in reading mode operation).
This first bias circuit 8 is a source of current-controlled voltage (if VB0=0, of course). The P type transistor 14a acts as a resistor, whereas transistors 15a and 15b operate in a feedback manner to keep the voltage at the control electrode of transistor 15b at a predictable potential. This in turn guarantees a predictable potential VB at the terminal 11. Should the resistance of transistor 14a vary with process, causing the current through transistor 14a to increase, the connection of transistor 15b causes the device 15a to decrease its current, which tends to counteract the original change. Thus, by negative feedback, it is ensured that there will be a precise and stable bias voltage VB available at the output 11.
The transistors 16b and 17 that are connected as diodes on the second arm 13 between the output terminal 11 and the ground terminal 5 enable the fixing of the bias voltage VB as a value equivalent to two threshold voltages Vt when VB0=0. The N type output transistor 18 enables the rapid pulling of the output terminal 11 to the ground potential GND when the connection between the floating-gate transistors 3 of the storage circuits 2 and the corresponding current sources (VB0=1) is cut. Furthermore, this makes it possible to ensure a known value of the voltage VB present at this time at the output terminal 11. This is important because it is possible that there might be a floating node at this place by parasitic capacitive effect.
FIG. 2A illustrates the temporal evolution of the output bias voltage VB using the circuit 8 in response to a step transition of VB0 from one to zero.
A present trend in the design of circuits 1 of the foregoing type leans towards the development of integrated circuits that work with variable supply voltage values. For example, circuits are being developed that can work as well with a 3-volt supply voltage as has been experienced with a 5-volt supply voltage. However, the bias circuit should be capable of supplying the positive bias voltage at high speed (typically within less than one xcexcsec). The bias circuit 8 described above is relatively fast and consumes little power when operating at five volts (see, FIG. 2A) . However, this circuit, along with other comparable biasing circuits, is not suitable for low supply voltages (for example, on the order of three volts) because their build-up time to VB unsatisfactorily exceeds one xcexcsec.
A second bias circuit 9 is accordingly provided to give a bias voltage to the isolation transistors having a response time constant that is relatively fast for supply voltages on the order of 3 volts. The second bias circuit 9 has an output terminal 19 and a control terminal 20. The input of an inverter 21 is connected to the control terminal 20. The output of this inverter 21 is connected to the output terminal 19 by means of a capacitor 22. The inverter 21 is made in a standard way by the series-connection of P and N type transistors 23 and 24 between a supply terminal 6 and a reference terminal 5.
The control terminal 20 of the second bias circuit 9 receives a second binary control signal VB0. The output terminal 19 of this second bias circuit supplies a binary bias voltage VB to the storage circuits 2. This bias voltage VB assumes a first binary value when the second control signal VB0 is in a first state (VB0=1) and a second binary value when said second control signal VB0 is in a second state (VB0=0).
FIG. 2B illustrates the temporal elevation of the output voltage VB using only the circuit 9 in response to a step transition of VB from one to zero.
Preferably, the output terminal 19 and the control terminal 20 of the second bias circuit 9 are connected to the corresponding terminals of the first bias circuit 8. Similarly, the supply terminal 6 and the ground terminal 5, as used by the two bias circuits 8 and 9, are identical.
FIG. 2C illustrates the temporal elevation of the output voltage VB when the circuits 8 and 9 are used together. This illustrates an improvement in response time (delta t) that is experienced with use of both circuits 8 and 9 in low voltage (for example, three volts) environment.
While the foregoing circuit 1 is relatively simple to implement and effectively provides extra current during charging time, the duration of the extra current that is supplied is controlled by an analog differentiation circuit that is somewhat uncorrelated with the capacitance of the bias voltage supply line leading to each of the circuits 2. This raises several concerns. First, the extra amount of charge that is supplied is mostly dependent upon the supply voltage and is therefore uncorrelated with bias voltage that is mostly constant. Second, the size of the boost capacitor 22 must be carefully chosen dependent on the size of the memory array. More specifically, it is recognized that the total capacitive load on the bias line is affected by both thin and thick oxide components. Accordingly, it is somewhat uncorrelated with the capacitance of the boost capacitor 22. If the boost capacitor 22 value is chosen too small, then inadequate extra charge is delivered during boost, and a slow response results. If, on the other hand, the boost capacitance value is too large (either from initial selection or process variations), then the bias voltage line will be boosted too much and extra time will be required to settle the bias voltage line back down to a desired voltage value. Third, the bias voltage itself is recognized to have a temperature coefficient. This means that the theoretically perfect amount of boost charge varies with temperature.
It is accordingly recognized that the prior art circuit of FIG. 1 suffers from a number of controllability concerns, and a need exists for a circuit that addresses these concerns while still being able to provide extra boost current needed to achieve a rapid response time.
A bias circuit includes a bias voltage generator and a boost circuit. The bias voltage generator produces a voltage signal that transitions from a first value to a second value in response to a change in a control signal. The boost circuit responds to the transition of the voltage signal from the first value by generating a boost current. The voltage signal and boost current are combined to provide an output bias voltage.
A method for generating an output bias voltage includes the step of generating a voltage signal that transitions from a first value to a second value in response to a change in a control signal. The transition of the voltage signal from the first value is then detected causing the generation of a boost current. The voltage signal and the boost current are then combined to provide an output bias voltage.